Exclusive OR Gate

The Exclusive OR/Exclusive NOR Gate models both a generic exclusive OR and exclusive NOR gate. The number of active-low inputs can be set to either 0 or 1. Both exclusive-OR and exclusive-NOR outputs are provided. The outputs change state at the same time, making the outputs perfectly complementary.

In this topic:

Model Name: Exclusive OR/Exclusive NOR Gate
Simulator: This device is compatible with the SIMPLIS simulator.
Parts Selector Menu Location: Digital Functions > Gates
Symbol Library: None - the symbol is automatically generated when placed or edited.
Model Library: SIMPLIS_DIGI1.LB
Subcircuit Names:
  • SIMPLIS_DIGI1_XOR_N : Without Ground Reference
  • SIMPLIS_DIGI1_XOR_Y : With Ground Reference
Symbol:
Without ground reference.
Multiple Selections: Only one device at a time can be edited.

Editing the Exclusive OR/Exclusive NOR Gate

To configure the Exclusive OR/Exclusive NOR Gate, follow these steps:

  1. Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Label Parameter Description
Propagation Delay Delay from when any input pin changes state until the outputs change state
# of Inverted Logic Inputs Number of active-low logic inputs. Any device can have active-low inputs up to the # of Logic Inputs minus 1.
Ground Ref Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic.
Initial Condition Initial condition of the Gate output at time=0

To define the parameters for the interface between this digital component and each analog component connected directly to an input or output pin, follow these steps:

  1. From the Edit Exclusive OR/Exclusive NOR Gate dialog box, click on the Interface tab.
  2. Make the appropriate changes to the fields described in the table below the image.
Label Parameter Description
Input Resistance Input resistance of each Gate input pin
Hysteresis, Threshold Hysteresis and Threshold of the inputs. The hysteretic-window width, HYSTWD is centered around Threshold (TH) voltage. To determine the actual threshold ( TL , THI ), substitute Threshold (TH) and Hysteresis (HYSTWD) in each of the following formulas:
Input Logic Level Actual Threshold
1 Threshold + 0.5 * Hysteresis
0 Threshold - 0.5 * Hysteresis
Output Resistance Output resistance of each Gate output pin
Output High Voltage Output high voltage for each Gate output pin
Output Low Voltage Output low voltage for each Gate output pin

Truth Table

The following truth table is for a two-input Exclusive-OR gate with active-high inputs.

Inputs Outputs
A B Exclusive-OR Exclusive-NOR
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1

Examples

The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_058_exclusiveorgate_example.sxsch.

Waveforms

The waveforms below were taken from an exclusive-OR gate with both inputs selected to be active high. With this configuration, the exclusive-OR output will be high when one, but not both, of the A and B inputs are high.

Subcircuit Parameters

The subcircuit parameters, parameter names, data types, ranges, units, and descriptions are in the following table. The parameter names can be used to directly generate netlist entries for the device. For example, the netlist entry for an exclusive-OR gate with active-high inputs and without ground reference would be as follows: 
X$U1 5 8 2 3 SIMPLIS_DIGI1_XOR_N vars: NumInv=0 IC=0 RIN=10Meg ROUT=10 HYSTWD=1 VOL=0 VOH=5 DELAY=2p TH=2.5
Parameter Name Label Data Type Range Units Parameter Description
DELAY Propagation Delay Number 1f to 1024 s Delay from when any input pin changes state until the outputs change state
GNDREF Ground Ref String
  • 'Y'
  • 'N'
 none Determines whether or not a device has a ground reference pin. Any digital component that has an input or output pin connected to an analog circuit node must have its Ground Ref pin connected to an analog node. This is usually the ground on the schematic.
HYSTWD,
TH		 Hysteresis,
Threshold		 Number min: 1f V Hysteresis and Threshold of the inputs. The hysteretic-window width, HYSTWD is centered around Threshold (TH) voltage. To determine the actual threshold ( TL , THI ), substitute Threshold (TH) and Hysteresis (HYSTWD) in each of the following formulas:
Input Logic Level Actual Threshold
1 Threshold + 0.5 * Hysteresis
0 Threshold - 0.5 * Hysteresis
IC Initial Condition Number
  • 0
  • 1
 none Initial condition of the Gate output at time=0
NUMINV # of Inverted Logic Inputs Number
  • 0
  • (# of Logic Inputs - 1)
 none Number of active-low logic inputs. Any device can have active-low inputs up to the # of Logic Inputs minus 1.
RIN Input Resistance Number min: 100 Ω Input resistance of each Gate input pin
ROUT Output Resistance Number min: 1m Ω Output resistance of each Gate output pin
VOH Output High Voltage Number any V Output high voltage for each Gate output pin
VOL Output Low Voltage Number any V Output low voltage for each Gate output pin