» SIMPLIS DVM Test Report Overview

General
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Testplan dvm_advanced.testplan
Original Testplan Filename line_and_load_regulation.testplan
Date / Time 2015-12-10 5:48 PM
Report Directory run_line_load_testplan
Log File dvm_advanced.log
# of Tests Run 7 of 7 (6 Passed, 1 Skipped)
Total Time 51s
Design Specifications
Circuit Name LTC3406B
Description Synchronous Buck
Input 1 5.000 V (4.5 V to 5.5 V)
Output 1 1.505 V (±5%) @ 1.5 A
Switching Frequency 955kHz
Calculated Results
Line and Load Regulation (Input 1, Output 1) 3.7136213%
Line Regulation (Input 1) for Output 1 0.0059800664%
Load Regulation (Output 1) for Output 1 0.0079734219%
Excel-compatible Results
Scalar Results dvm_advanced_table_scalars.txt
Spec Results dvm_advanced_table_specs.txt
Statistic Results dvm_advanced_table_statistics.txt
Statistic Specs dvm_advanced_table_statspecs.txt
Test 1 of 7top ▲
Test Label Steady-State|Input 1 Minimum Voltage, Output 1 100% Load
Simulator simplis
Test Report Steady-State\Input1 Minimum Voltage, Output 1 100% Load\report.txt.html
Status PASS
Test Time 8s
Test 2 of 7top ▲
Test Label Steady-State|Input 1 Maximum Voltage, Output 1 Light Load
Simulator simplis
Test Report Steady-State\Input1 Maximum Voltage, Output 1 Light Load\report.txt.html
Status PASS
Test Time 8s
Test 3 of 7top ▲
Test Label Steady-State|Input 1 Nominal Voltage, Output 1 100% Load
Simulator simplis
Test Report Steady-State\Input1 Nominal Voltage, Output 1 100% Load\report.txt.html
Status PASS
Test Time 8s
Test 4 of 7top ▲
Test Label Steady-State|Input 1 Nominal Voltage, Output 1 Light Load
Simulator simplis
Test Report Steady-State\Input1 Nominal Voltage, Output 1 Light Load\report.txt.html
Status PASS
Test Time 8s
Test 5 of 7top ▲
Test Label Steady-State|Input 1 Minimum Voltage, Output 1 50% Load
Simulator simplis
Test Report Steady-State\Input1 Minimum Voltage, Output 1 50% Load\report.txt.html
Status PASS
Test Time 7s
Test 6 of 7top ▲
Test Label Steady-State|Input 1 Maximum Voltage, Output 1 50% Load
Simulator simplis
Test Report Steady-State\Input1 Maximum Voltage, Output 1 50% Load\report.txt.html
Status PASS
Test Time 8s
Test 7 of 7top ▲
Test Label Final Math
Simulator N/A
Test Report FinalMath\report.txt.html
Status SKIP
Test Time 0s