SystemDesigner Subtractor

The SystemDesigner Subtractor models a subtraction operation of two SystemDesigner buses, with a 32-bit signed-integer or floating-point result. From the Output parameter box, you can limit the resulting output to either signed or unsigned numbers with fewer than 32 bits.

The propagation delay can be defined as a fixed time, as asynchronous to any clock, or as a synchronous delay where the delay is a number of SystemDesigner -clocks cycles. In this release of SystemDesigner , the synchronous delay is supported only for integer-sampled data simulations.

In this topic:

Model Name:

Simulator:

This device is compatible with the SIMPLIS simulator.

Parts Selector Menu Location:

SystemDesigner Functions (max. 32 bit) > Arithmetic

Symbol Library:

SIMPLIS_SystemDesigner.sxslb

Model Library:

SIMPLIS_SystemDesigner.lb

Subcircuit Names:

SIMPLIS_SD_SUBTRACTOR_32x32 : 2-input subtractor
SIMPLIS_SD_SUBTRACTOR_32x32x32 : 3-input subtractor

Symbols:

	2-input subtractor
	2-input subtractor, alternate pin location
	3-input subtractor

Multiple Selections:

Only one device at a time can be edited.

Editing the SystemDesigner Subtractor

To configure the SystemDesigner Subtractor, follow these steps:

Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
Make the appropriate changes to the fields described in the table below the image.

Label	Parameter Description
Use asynchronous delay	Implements a combinatorial model where the output voltage changes in response to the input voltage change after a propagation delay.
Propagation delay	The propagation delay from an input change to an output change in seconds. This parameter is used only in models with Asynchronous delay.
Use synchronous delay	In response to an input voltage change, the output voltage changes after a designated number of clock cycles.
Delay	The propagation delay from an input change to an output change in number of clock cycles. The output will not change until the number of clock cycles has been reached. The output will then change state only on the selected Clock source edges specified by Trigger edge . This parameter is used only in models with Synchronous delay.
Clock source	Specifies the global clock used for the Subtractor. The Clock can be set up using the SystemDesigner->Edit SystemDesigner Clocks... menu item or by placing a Start of Conversion Breakin.
Trigger edge	Sets the Subtractor output to change on specific edges of the Clock: 0_TO_1 The output changes only on rising edges of the Clock source 1_TO_0 The output changes only on falling edges of the Clock source
Use 32 bit signed	The full 32-bit signed data is output.
Limit output to:	The output is limited to a Signed or Unsigned number with a designated number of bits.
Number type	The output will be limited to either a Signed or Unsigned number if Limit output to is selected. Signed numbers include integers from -2^{Number of bits-1} to 2^{Number of bits-1} -1 Unsigned numbers include integers from 0 to 2^{Number of bits} This parameter is used only in models with Limit output to selected.
Number of bits	The limit on the output depends on the Number type parameter: Signed numbers include integers from -2^{Number of bits-1} to 2^{Number of bits-1} -1 Unsigned numbers include integers from 0 to 2^{Number of bits} This parameter is used only in models with Limit output to selected.
Initial Condition	Initial condition of the output at time=0. Value is the output bus represented in decimal format.

Examples

The subtractor circuit used to generate the following waveforms can be downloaded here: simplis_111_systemdesigner_subtractor_example.sxsch. In order to simulate this design, follow these steps:

If you currently have a dialog box open in SIMetrix/SIMPLIS, cancel that dialog box so that the example can open in SIMetrix/SIMPLIS.
Unzip the archive to a location on your computer.
To open the schematic, double click the .sxsch file or drag that file into the SIMetrix/SIMPLIS Command Shell.

Waveforms

The subtractor example below is taken from part of the SystemDesigner DPWM Example. In this example, the subtractor with reference SUBTRACTOR_1 subtracts the last error (Error N1) from the current error (Error N0) and outputs the difference.

The Input voltage to the ADC is a sine wave with the following parameters:

Amplitude = +/- 5.1mV
Period = 40us
Delay =10us.
During the delay time, the sine wave source has a value of zero volts.

During integer-sampled data simulations, the sine wave voltage is sampled by the ADC and quantized into BIN_SIZE amplitude values. The BIN_SIZE is set to 2mV with a variable in the F11 window of the schematic. The quantized amplitude of both Error signals has a maximum value of 3 LSB counts, which is plotted with a 2m gain, effectively scaling the sampled error voltages to the same amplitude as the input to the ADC. On the waveforms below, 2mV is, therefore, equivalent to the LSB count. The unit delay block then delays the current error by 1 clock cycle, which in this case is 2us. The subtractor then subtracts the two errors producing:
Difference = Error N1 - Error N0.

For double-precision floating-point sampled-data simulations, the ADC behaves as a sample/hold and gains the result by 1/BIN_SIZE, which, with a BIN_SIZE of 2mV is a gain of 500. The output of the ADC is therefore a sampled-time analog voltage, but without amplitude quantization. The peak amplitude of the ADC is 5.1mV * 1/BIN_SIZE or 2.55V. Notice the difference between this error and the error for the integer-data simulation. In the integer simulation, the Error N0 signal takes on discrete amplitudes, whereas in the floating point simulation, the amplitudes are not quantized. The ADC output is then input to the unit delay which then delays the analog signal one clock cycle. The subtractor then subtracts the two analog signals and produces the output: Difference = Error N1 - Error N0.

The AC transfer function for the subtractor circuit is shown below. As expected, the transfer function is that of a differentiator.