Unit Delay

The Unit Delay models a single clock cycle delay in the z-domain. The transfer function in the z-domain from the input I(z) to the output O(z) for the Unit Delay is shown below:

The difference equation representing this transfer function is

As with the other devices in the Discrete Time Filter category, the Unit Delay is compatible with the SIMPLIS POP and AC Analyses.

The information in this topic refers to the latest Unit Delay which was introduced in version 8.10. In versions prior to 8.10, a similar Unit Delay exists; however, this unit delay has different behavior than the current unit delay. When using the old unit delay, depending on how the system containing the unit delay is clocked, the unit delay may delay the signal two clock periods. This has been corrected in the new unit delay.

If you require a unit delay for use in versions prior to 8.10, the old Unit Delay can be placed from the part selector location: Obsolete > Digital Functions > Unit Delay (Obsolete) .

Related topics:

• SIMPLIS Discrete Time Filters
• Discrete IIR Filters Versus Discrete FIR Filters

Model Name:	Unit Delay
Simulator:		This device is compatible with the SIMPLIS simulator.
Parts Selector Menu Location:	Digital Functions > Discrete Time Filters
Symbol Library:	simplis_discrete_time_filters.sxslb
Model Library:	simplis_discrete_time_filters.lb
Subcircuit Name:	SIMPLIS_DTF_UNIT_DELAY_Y__V2
Symbol:
Multiple Selections:	Only one device at a time can be edited.

Editing the Unit Delay

To configure the Unit Delay, follow these steps:

1. Double click the symbol on the schematic to open the editing dialog to the Parameters tab.
2. Make the appropriate changes to the fields described in the table below the image.

Label	Parameter Description
Acquisition Time	Filter acquisition time in seconds
Initial Condition	Initial condition of the Unit Delay output at time=0

Examples

The test circuit used to generate the waveform examples in the next section can be downloaded here: simplis_037_unitdelay_example.sxsch.

Waveforms

In the circuit example, a 100kHz sine wave with a 1V amplitude (+/- 1V peak) is applied to the input of the Unit Delay. The clock has a frequency of 1MHz, and the sampled input voltage is output on the same graph as the input voltage.

The following AC waveforms confirm that the DC gain is 0dB and that the phase change at 1/2 the sampling frequency is the expected 270 degrees.

X$U1 33 35 0 34 0 SIMPLIS_DTF_UNIT_DELAY_Y__V2 vars: IC=0 T_ACQ=1n