SystemDesignerdistributes global clocks to every SystemDesigner component. Although most designs require only a single system clock, having lower or higher frequency clocks may be useful in some cases.
You can define up to eight clocks (SysCLK plus User1 through User7) as shown in the dialog and explained in the table below.
|Column||Edit control type||Definition|
|Enable||CheckBox||Enables each clock. Disabled clocks are not included in the simulation.|
|Graph||CheckBox||If checked, the clock waveform appears in the graph viewer. Clocks need not be graphed to use on the schematic.|
|Label||String||The label assigned to the curve. The label cannot contain spaces.|
|Frequency (Hz)||String||The clock frequency in Hz.|
|Duty cycle (%)||String||The clock duty cycle in percent.|
|Delay (s)||String||The delay in seconds. If the delay is less than 0, each clock is given a delay = 0.5 times the highest frequency clock period.|
To define and edit a SystemDesigner clock, follow these steps:
Each system clock (SykCLK, User1 through User7) is assigned a vertical order string = clk n , where "n" is 0 through 7. To change the default order of the system clocks, follow these steps:
If you want to include probes in the graph viewer, you can assign a string to the probe in order to place it either above or below the system clocks. Since each system clock label begins with a c, use the following approach to define the placement of probes on the graph.
To assign a Display order string to the SystemDesigner bus probe, follow these steps:
To define the order of other probes, double click the probe and set the Display order in the same way as you set the SystemDesigner bus probe. For the Display order to take effect, the other probes must be output to the digital axis.
From the Edit SystemDesigner Clocks dialog, you use the Close and Graph Clocks button to run a simulation on the clocks defined in that dialog. No components from the currently selected schematic will be included in this simulation.
For example, the following dialog has three system clocks defined:
To save the clock information and simulate those three clocks, click Close and Graph Clocks.
If you want to expose a global clock to a schematic, a special symbol, the SystemDesigner Global Clock Breakout, is available to expose the global clock on a symbol pin that can be wired to any analog or digital component on the schematic, such as the one below.
In this example, two global clocks have been exposed through the SystemDesigner Global Clock Breakout devices, and connected to regular voltage probes. A SystemDesigner Constant has also been placed on the schematic, and a SystemDesigner bus probe has been added to plot the constant value. Each probe has been assigned a Display order string of a, b, or z.
The resulting graphs show the probes in the correct vertical order.
Digital waveforms are ordered alphabetically by the Display order string.