Module 1 lays the groundwork for the entire course, by whetting the attendee's appetite through examples and exercises.
In the first section, a number of examples compare and contrast SIMPLIS with more common SPICE-based simulators. Models designed for SIMPLIS use Piecewise Linear (PWL) modeling, and the basics of PWL modeling and the accuracy of PWL models are discussed. The Periodic Operating Point (POP) analysis, which is unique to SIMPLIS is introduced and the AC analysis on the time-domain PWL model is also covered. A brief introduction to the Design Verification Module (DVM) prepares users to automate model testing.
The second section gives the briefest introduction to the Design Verification module (DVM). DVM allows you to run a schematic design through a set of tests to verify the design meets design specification.
The third section describes how the user interface is constructed. In this section, you will learn how to customize the SIMetrix/SIMPLIS interface with new menu items and keyboard shortcuts.
By the end of this module you will understand the basic framework on which all of the following training modules are based.
While the class is getting settled:
|1.1_SelfOscillatingConverter_POP_AC_Tran.sxsch||POP, AC, and Transient Analyses, PWL Models|
|1.2_SIMPLIS_tutorial_buck_converter.sxsch||POP, AC, and Transient Analyses, PWL Models|
|1.4_PFC_Critical_Conduction_Mode.sxsch||Probe measurements, per cycle measurements|
||Introduction to the SIMPLIS Digital libraries|
|1.7_simplis_042_lut_dont_care_example.sxsch||The power of Digital Look Up Tables|
|1.8_simplis_002_constant_power_load_example.sxsch||The power of PWL modelling|
|1.9_SIMPLIS_Multiplication.sxsch||A case study of multiplication methods|
||Use of POP/AC Analysis for a class D amplifier|
|1.13_LTC3406B - DVM ADVANCED.sxsch||General purpose DVM schematic|
|1.14_LTC3406B-CurrentLimit.sxsch||Current limit behavior DVM schematic|
|1.15_PWL_Capacitor.sxsch||Non-linear diode capacitance using a PWL capacitor|
|1.16_vpwl_ipwl_resistors.sxsch||Current limit behavior DVM schematic|
|1.17_simplis_007_multi_level_pwl_capacitor_example.sxsch||MLCC PWL capacitor example w/ error compared to data sheet|
|1.18_simplis_008_multi_level_pwl_inductor_example.sxsch||PWL inductor example w/ Flux error compared to data sheet|
Module 1 includes the following topics:
At the end of the module, please fill out the Module # 1 Evaluation form.