In the 1.0 SIMPLIS Basics topics you learned how SIMPLIS simulates circuits in the time domain using the POP, Transient and AC analyses. Using the example circuits, you ran single simulations using combinations of the three SIMPLIS analysis types. The Design Verification Module automates testing on a circuit, running multiple tests and aggregating scalar and waveform results in a HTML report file.
In this topic:
This topic addresses the following key concepts:
In this topic, you will learn the following:
DVM contains several built-in testplans for AC/DC and DC/DC converters. These testplans can be run on any schematic which has been converted to run in DVM. Converting a schematic to run in DVM only requires you to replace the input source symbol and output load resistor with DVM source and load symbols and then add a DVM control symbol to the schematic. An example schematic prepared for DVM is included in the Module 1 Examples - 1.13_LTC3406B - DVM ADVANCED.sxsch.
The dialog will look similar to the following:
The Design Verification Module allows a user to setup and run multiple tests on a design in 5 minutes or less. The built-in testplans speed up the process by configuring the sources and loads as well as setting the analysis statements. DVM also makes scalar measurements and checks specification values to determine the pass/fail status of each test. Each built-in testplan covers a logical combination of input voltage and output load conditions, and is quite comprehensive. For example, the built-in testplan you just ran has 129 tests in total. On a reasonably powerful machine, a user can execute all 129 tests in this testplan in around 20 minutes on this model.
The only goal in this section is to make you aware that this kind of automation tool exists and is in use, perhaps by your customers. As a result, one of your customers could very easily convert your schematics to run in DVM and automate running simulations on the design.
These customers verify their designs with exhaustive simulation testing, especially where the cost of failure is very high. Their design verification test protocols include hundreds of simulations that must be analyzed and summarized. These design verification tests put a lot of strain on simulation models in terms of both accuracy and speed.
DVM provides a first level screen that demonstrates how well your model performs. If your model will successfully run the appropriate built-in testplan in a modest amount of time, it has passed the first test. If it took a day to complete, well, you have more work to do!
The capabilities of DVM are much larger than the built-in testplans. Included in the examples zip file is an example titled 1.14_LTC3406B-CurrentLimit.sxsch. This schematic and the custom testplan generated for it: current_limit_1in_1out.testplan, which is in the testplans folder, explores the current limit behavior of the power supply. The testplan runs through a sequence of POP simulations where the output of the power supply is forced to a known voltage. Each test changes the output voltage, and after all tests complete, the average output voltage vs. average output current is plotted on a x-y graph. This is one of many advanced simulation scenarios which DVM can facilitate.