Flip-Flops and Latches

D-type Flip Flop

Netlist entry

Axxxx data clk set reset out nout model_name

Connection details

Model format

.MODEL model_name d_dff parameters

Model parameters

Device Operation

This device has been superseded by Universal Flip-flop using model parameter "type=D".

The device is an edge triggered D-type flip flop with active high asynchronous set and reset. The operation of the device is illustrated by the following diagram:

D-type Latch

Netlist entry

Axxxx data enable set reset out nout model_name

Connection details

Model format

.MODEL model_name d_dlatch parameters

Model parameters

Device Operation

This device has now been superseded by D-type Latch (New).

The device is a level triggered latch with a single data input, complimentary outputs and active high asynchronous set and reset. The operation of the device is illustrated in the following diagram:

The asynchronous inputs (set and reset) override the action of the enable and data lines.

D-type Latch (New)

This device has the same functionality as the older D-type Latch (D-type Latch) but this newer version implements signal delays in a manner that is more representative of real devices and is recommended for new designs. The generic D-type latch available in the schematic editor uses this device.

Netlist entry

Axxxx data enable set reset out nout model_name

Connection details

Model format

.MODEL model_name d_latch parameters

Model parameters

Device Operation

The device is a level triggered latch with a single data input, complimentary outputs and active high asynchronous set and reset. The operation of the device is illustrated in the following diagram:

Note that any signal on the enable, set, reset or data that is shorter than the associated delay time will not be actioned. So for example, if the enable_delay parameter is set to 10ns, a 9.9ns pulse on the enable input will not enable the latch whereas a 10.1ns pulse will enable the latch. This behaviour is the important difference between this device and the older D-type latch.

The asynchronous inputs (set and reset) override the action of the enable and data lines.

JK Flip Flop

Netlist entry

Axxxx j k clk set reset out nout model_name

Connection details

Model format

.MODEL model_name d_jkff parameters

Model parameters

Device Operation

This device has been superseded by Universal Flip-flop using model parameter "type=JK".

The following circuit and graph illustrate the operation of this device:

The following table describes the operation of the device when both inputs are at known states: The output can only change on a positive edge of the clock.

Set-Reset Flip-Flop

Netlist entry

Axxxx s r clk set reset out nout model_name

Connection details

Model format

.MODEL model_name d_srff parameters

Model parameters

Device Operation

This device has been superseded by Universal Flip-flop using model parameter "type=SR".

The SR flip flop is similar to a JK flip flop except that the output is UNKNOWN when both S and R inputs are high. In a JK the output toggles in the same circumstances.

The following table describes the operation of the device when both inputs are at known states: The output can only change on a positive edge on the clock.

SR Latch

Netlist entry

Axxxx s r enable set reset out nout model_name

Connection details

Model format

.MODEL model_name d_srlatch parameters

Model parameters

Device Operation

This device is identical to the SR flip flop except that it is level not edge triggered. That is the output may change whenever the enable input is high.

Toggle Flip Flop

Netlist entry

Axxxx t clk set reset out nout model_name

Connection details

Model format

.MODEL model_name d_tff parameters

Model parameters

Device Operation

This device has been superseded by Universal Flip-flop using model parameter "type=T".

The operation of the toggle flip flop is illustrated by the following diagrams. When the T input is high, the output toggles on each rising edge of the clock. If the T input is UNKNOWN the output will be UNKNOWN.

Universal Flip-flop

Overview

The universal flip-flop is a general purpose edge-triggered device which can be configured in one of four types. These are D-type, JK, Toggle and SR. The device has more timing control parameters than the older dedicated types and it is recommended that this device is used for all new designs.

Netlist entry

Axxxx in out model_name

Connection details

Model format

.MODEL model_name d_flipflop parameters

Model parameters

Model Parameter Notes

Timings

Setup and Hold Time

The diagram above illustrates setup time, hold time and total clock delay. The data input must not change between the setup time before the clock edge to the hold time after the clock edge in order for the data value to be clocked. If this condition is violated the flip-flop will not change state.

Asynchronous Set/Reset Timings

The diagram above illustrates the aynchronous set/reset timing and its interaction with clock timing. The set and reset signals must be inactive prior to the clock edge, the margin allowed being the removal time (rem_time parameter). If this condition is violated, the subsequent clock edge will be inactive but the set/reset will be successful as long as the minimum pulse width condition is satisfied.

Operation

This device implements four types of edge triggered flip-flop, namely D, T (toggle), J-K and S-R. The type of flip-flop is controlled by the type parameter.

Operation - D-type

On the active clock edge the state of the flip flop acquires the state of the single D input provided the setup and hold times are met. If the D input has an UNKNOWN state, the flip-flop state will also acquire an UNKNOWN state.

Operation - T toggle Flip-Flop

If the single T input is at a logic ONE, the state of the flip-flop inverts on the active clock edge. If the input is at a logic zero, the state remains unchanged.

Operation - J-K Flip-Flop

The J-K flip flop has two inputs. The operation is defined by the following table:

The above table describes the operation for the normal situation when both inputs are in known (ZERO or ONE) states. The complete table including also UNKNOWN states is shown below. In some cases a known state can be clocked even if one of the inputs is unknown.

Operation SR Flip-Flop

The SR flip flop has two inputs. The operation is defined by the following table:

The above table describes the operation for the normal situation when both inputs are in known (ZERO or ONE) states. The complete table including also UNKNOWN states is shown below.