Review: Creating MOSFET Models For SIMPLIS

Two key concepts were presented in the previous webinar:

  1. Parameter extracted MOSFETs in SIMPLIS do NOT include parasitic lead inductance.
    • Some SPICE models include lead inductance and some do not.
  2. You should verify the accuracy of the SPICE model
    • Pay close attention to CDG when VGS > VDS
    • Verify that extracted capacitance curves match the datasheet

Once lead inductance and the non-linear CDG capacitance when VDG < 0 is taken into account, its straightforward to match the simulated losses in SIMPLIS and SPICE to less than 2%