back to overview ▲

» DVM Test Report: VOUT=0.6V|Bode Plot|Vin Nominal|50% Load

Test Details
Schematic 6.3_LTC3406B - DVM ADVANCED.sxsch
Test VOUT=0.6V|Bode Plot|Vin Nominal|50% Load
Date / Time 12/10/2015 5:55 PM
Report Directory use_extract_curve\VOUT=0.6V\BodePlot\Vin Nominal\50% Load
Log File report.txt
Screenshot schematic.png
Status FAIL
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 77.0246%
Frequency(CLK) 955.694k
gain_crossover_freq 20.0176k
gain_margin 33.6973
ILOAD
AVG
301.714m
MIN
300.515m
MAX
302.461m
RMS
301.715m
PK2PK
1.94588m
ISRC
AVG
47.435m
MIN
423.251u
MAX
511.753m
RMS
127.836m
PK2PK
511.33m
min_phase 39.7137
min_phase_freq 20.0176k
phase_crossover_freq 338.909k
phase_margin 39.7042
Power(LOAD) 182.671m
Power(SRC) 237.159m
VLOAD
AVG
605.44m
MIN
603.035m
MAX
606.94m
RMS
605.442m
PK2PK
3.90473m
VSRC
AVG
4.99995
MIN
4.99949
MAX
5
RMS
4.99995
PK2PK
511.33u
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (606.94m) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD FAIL: Min. Output1 Voltage (603.035m) is not greater than or equal to Min. Output1 Voltage Spec (1.42975)
min_gain_margin PASS: Gain Margin (33.6973) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (39.7042) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac4_197.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop5_180.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop5_170.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop5_175.sxgph
Other SXGPH Files
clock#pop simplis_pop5_162.sxgph