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» DVM Test Report: Steady-State|Steady-State|Vin Minimum|30%

Test Details
Schematic 4.2_LTC3406B - DVM ADVANCED.sxsch
Test Steady-State|Steady-State|Vin Minimum|30%
Date / Time 12/10/2015 5:47 PM
Report Directory run_blt_in_and_prmt_grphs\Steady-State\Steady-State\VinMinimum\30%
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 85.5263%
Efficiency_Min 85.5263%
Frequency(CLK) 955.656k
ILOAD
AVG
450.184m
MIN
449.117m
MAX
451.099m
RMS
450.185m
PK2PK
1.98254m
ISRC
AVG
176.132m
MIN
381.003u
MAX
706.154m
RMS
297.581m
PK2PK
705.773m
Power(LOAD) 677.801m
Power(SRC) 792.505m
VLOAD
AVG
1.5056
MIN
1.50203
MAX
1.50866
RMS
1.50561
PK2PK
6.63043m
VSRC
AVG
4.49982
MIN
4.49929
MAX
4.5
RMS
4.49982
PK2PK
705.773u
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (1.50866) is less than or equal to Max. Output1 Voltage Spec (1.58025)
Min_VLOAD PASS: Min. Output1 Voltage (1.50203) is greater than or equal to Min. Output1 Voltage Spec (1.42975)
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop26_894.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop26_884.sxgph
default
CLK
ILOUT
SW
VOUT
SXGPH File simplis_pop26_889.sxgph
Other SXGPH Files
clock#pop simplis_pop26_876.sxgph