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» DVM Test Report: VOUT=1.505V|Bode Plot|Vin Nominal|Light Load
| Test Details | |
| Schematic | 6.3_LTC3406B - DVM ADVANCED.sxsch |
| Test | VOUT=1.505V|Bode Plot|Vin Nominal|Light Load |
| Date / Time | 12/10/2015 5:56 PM |
| Report Directory | promote_graphs\VOUT=1.505V\BodePlot\Vin Nominal\Light Load |
| Log File | report.txt |
| Screenshot | schematic.png |
| Status | FAIL |
| Simulator | simplis |
| Deck | input.deck |
| Init | input.deck.init |
| Measured Scalar Values | |
| Efficiency | 91.1062% |
| Frequency(CLK) | 955.703k |
| gain_crossover_freq | 13.4247k |
| gain_crossover_freq_nom | 13.4247k |
| gain_margin | 49.9661 |
| gain_margin_nom | 49.9661 |
| ILOAD | AVG 50.0255m MIN 49.9785m MAX 50.0675m RMS 50.0255m PK2PK 88.9653u |
| ISRC | AVG 16.5357m MIN 287.388u MAX 500.173m RMS 52.2926m PK2PK 499.886m |
| min_phase | 11.5623 |
| min_phase_freq | 6.30957k |
| phase_crossover_freq | 642.362k |
| phase_margin | 14.8135 |
| phase_margin_nom | 14.8135 |
| Power(LOAD) | 75.3225m |
| Power(SRC) | 82.6755m |
| VLOAD | AVG 1.50568 MIN 1.50427 MAX 1.50695 RMS 1.50568 PK2PK 2.67763m |
| VSRC | AVG 4.99998 MIN 4.9995 MAX 5 RMS 4.99998 PK2PK 499.886u |
| Measured Spec Values | |
| Max_VLOAD | PASS: Max. Output1 Voltage (1.50695) is less than or equal to Max. Output1 Voltage Spec (1.58025) |
| Min_VLOAD | PASS: Min. Output1 Voltage (1.50427) is greater than or equal to Min. Output1 Voltage Spec (1.42975) |
| min_gain_margin | PASS: Gain Margin (49.9661) is greater than Min. Gain Margin (12) |
| min_phase_margin | FAIL: Phase Margin (14.8135) is not greater than Min. Phase Margin (35) |
 Bode Plot
GAIN
PHASE
|
|
| SXGPH File | simplis_ac1_36.sxgph |
 LOAD
VLOAD
ILOAD
|
|
| SXGPH File | simplis_pop1_19.sxgph |
 SRC
VSRC
ISRC
|
|
| SXGPH File | simplis_pop1_9.sxgph |
 default
CLK
ILOUT
SW
VOUT
|
|
| SXGPH File | simplis_pop1_14.sxgph |
| Other SXGPH Files | |
| clock#pop | simplis_pop1_1.sxgph |
