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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|60% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|60% Load
Date / Time 12/10/2015 6:09 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\60% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.6965%
eta_nom 95.6965%
Frequency(CLK) 86.4955k
gain_crossover_freq 4.89133k
gain_margin 21.776
gmargin_nom 21.776
gxover_nom 4.89133k
ILOAD
AVG
3.0125
MIN
3.00875
MAX
3.01486
RMS
3.0125
PK2PK
6.1187m
iload_nom 3.0125
ISRC
AVG
199.662m
MIN
-534.74m
MAX
824.121m
RMS
413.53m
PK2PK
1.35886
min_phase 43.0874
min_phase_freq 4.89133k
phase_crossover_freq 22.0379k
phase_margin 42.774
pmargin_nom 42.774
Power(LOAD) 72.5901
Power(SRC) 75.8545
sw_freq_nom 86.4955k
VLOAD
AVG
24.0963
MIN
24.0664
MAX
24.115
RMS
24.0963
PK2PK
48.6869m
VSRC
AVG
379.98
MIN
379.918
MAX
380.053
RMS
379.98
PK2PK
135.886m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.115) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0664) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (21.776) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (42.774) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac10_594.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop10_560.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop10_550.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop10_541.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop10_555.sxgph
Other SXGPH Files
default#583#pop simplis_pop10_583.sxgph
Modulator#pop simplis_pop10_588.sxgph