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» DVM Test Report: Efficiency and Loop Characterization|Vin Nominal|50% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Nominal|50% Load
Date / Time 12/10/2015 6:08 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Nominal\50% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.8107%
eta_nom 95.8107%
Frequency(CLK) 86.8101k
gain_crossover_freq 4.83828k
gain_margin 23.6665
gmargin_nom 23.6665
gxover_nom 4.83828k
ILOAD
AVG
2.51056
MIN
2.50795
MAX
2.51226
RMS
2.51056
PK2PK
4.3141m
iload_nom 2.51056
ISRC
AVG
166.199m
MIN
-534.099m
MAX
746.728m
RMS
374.24m
PK2PK
1.28083
min_phase 45.8063
min_phase_freq 4.83828k
phase_crossover_freq 25.2744k
phase_margin 45.5353
pmargin_nom 45.5353
Power(LOAD) 60.4964
Power(SRC) 63.1416
sw_freq_nom 86.8101k
VLOAD
AVG
24.0968
MIN
24.0719
MAX
24.1131
RMS
24.0968
PK2PK
41.1418m
VSRC
AVG
379.983
MIN
379.925
MAX
380.053
RMS
379.983
PK2PK
128.083m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1131) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0719) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (23.6665) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (45.5353) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac9_534.sxgph
LOAD
ILOAD
VLOAD
SXGPH File simplis_pop9_500.sxgph
SRC
ISRC
VSRC
SXGPH File simplis_pop9_490.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop9_481.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop9_495.sxgph
Other SXGPH Files
default#523#pop simplis_pop9_523.sxgph
Modulator#pop simplis_pop9_528.sxgph