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» DVM Test Report: Efficiency and Loop Characterization|Vin Minimum|35% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Minimum|35% Load
Date / Time 12/10/2015 6:15 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\35% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.8025%
eta_min 95.8025%
Frequency(CLK) 79.7164k
gain_crossover_freq 4.83002k
gain_margin 25.9067
gmargin_min 25.9067
gxover_min 4.83002k
ILOAD
AVG
1.75744
MIN
1.75616
MAX
1.75854
RMS
1.75744
PK2PK
2.38225m
iload_min 1.75744
ISRC
AVG
122.817m
MIN
-575.917m
MAX
659.923m
RMS
335.671m
PK2PK
1.23584
min_phase 45.6699
min_phase_freq 4.83002k
phase_crossover_freq 30.3318k
phase_margin 45.4158
pmargin_min 45.4158
Power(LOAD) 42.3473
Power(SRC) 44.2027
sw_freq_min 79.7164k
VLOAD
AVG
24.096
MIN
24.0785
MAX
24.1109
RMS
24.096
PK2PK
32.3495m
VSRC
AVG
359.988
MIN
359.934
MAX
360.058
RMS
359.988
PK2PK
123.584m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1109) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0785) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (25.9067) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (45.4158) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac35_2094.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop35_2060.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop35_2050.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop35_2041.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop35_2055.sxgph
Other SXGPH Files
default#2083#pop simplis_pop35_2083.sxgph
Modulator#pop simplis_pop35_2088.sxgph