Test Details | |
Schematic | 8.2_LLC Closed Loop.sxsch |
Test | Efficiency and Loop Characterization|Vin Minimum|15% Load |
Date / Time | 12/10/2015 6:14 PM |
Report Directory | measure_loop_param\Efficiencyand Loop Characterization\Vin Minimum\15% Load |
Log File | report.txt |
Screenshot | schematic.png |
Status | PASS |
Simulator | simplis |
Deck | input.deck |
Init | input.deck.init |
Measured Scalar Values | |
Efficiency | 95.4181% |
eta_min | 95.4181% |
Frequency(CLK) | 80.4204k |
gain_crossover_freq | 4.33243k |
gain_margin | 26.59 |
gmargin_min | 26.59 |
gxover_min | 4.33243k |
ILOAD | AVG 753.473m MIN 753.232m MAX 753.76m RMS 753.473m PK2PK 528.069u |
iload_min | 753.473m |
ISRC | AVG 52.8774m MIN -574.329m MAX 579.538m RMS 277.052m PK2PK 1.15387 |
min_phase | 63.9979 |
min_phase_freq | 4.33243k |
phase_crossover_freq | 32.444k |
phase_margin | 63.6871 |
pmargin_min | 63.6871 |
Power(LOAD) | 18.1563 |
Power(SRC) | 19.0282 |
sw_freq_min | 80.4204k |
VLOAD | AVG 24.0968 MIN 24.0893 MAX 24.1058 RMS 24.0969 PK2PK 16.5182m |
VSRC | AVG 359.995 MIN 359.942 MAX 360.057 RMS 359.995 PK2PK 115.387m |
Measured Spec Values | |
Max_VLOAD | PASS: Max. Output1 Voltage (24.1058) is less than or equal to Max. Output1 Voltage Spec (25.2) |
Min_VLOAD | PASS: Min. Output1 Voltage (24.0893) is greater than or equal to Min. Output1 Voltage Spec (22.8) |
min_gain_margin | PASS: Gain Margin (26.59) is greater than Min. Gain Margin (12) |
min_phase_margin | PASS: Phase Margin (63.6871) is greater than Min. Phase Margin (35) |
Bode Plot
GAIN
PHASE
|
|
SXGPH File | simplis_ac31_1854.sxgph |
LOAD
VLOAD
ILOAD
|
|
SXGPH File | simplis_pop31_1820.sxgph |
SRC
ISRC
VSRC
|
|
SXGPH File | simplis_pop31_1810.sxgph |
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
|
|
SXGPH File | simplis_pop31_1801.sxgph |
Secondary
CLK
ICout
Is1
Is2
Vs
|
|
SXGPH File | simplis_pop31_1815.sxgph |
Other SXGPH Files | |
default#1843#pop | simplis_pop31_1843.sxgph |
Modulator#pop | simplis_pop31_1848.sxgph |