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» DVM Test Report: Efficiency and Loop Characterization|Vin Maximum|70% Load

Test Details
Schematic 8.2_LLC Closed Loop.sxsch
Test Efficiency and Loop Characterization|Vin Maximum|70% Load
Date / Time 12/10/2015 6:12 PM
Report Directory measure_loop_param\Efficiencyand Loop Characterization\Vin Maximum\70% Load
Log File report.txt
Screenshot schematic.png
Status PASS
Simulator simplis
Deck input.deck
Init input.deck.init
Measured Scalar Values
Efficiency 95.6179%
eta_max 95.6179%
Frequency(CLK) 94.1424k
gain_crossover_freq 5.17064k
gain_margin 22.6043
gmargin_max 22.6043
gxover_max 5.17064k
ILOAD
AVG
3.51421
MIN
3.50911
MAX
3.51695
RMS
3.51421
PK2PK
7.83759m
iload_max 3.51421
ISRC
AVG
221.43m
MIN
-665.282m
MAX
896.958m
RMS
450.763m
PK2PK
1.56224
min_phase 61.6285
min_phase_freq 5.17064k
phase_crossover_freq 25.8905k
phase_margin 61.3474
pmargin_max 61.3474
Power(LOAD) 84.6714
Power(SRC) 88.5518
sw_freq_max 94.1424k
VLOAD
AVG
24.094
MIN
24.0592
MAX
24.1127
RMS
24.094
PK2PK
53.5341m
VSRC
AVG
399.978
MIN
399.91
MAX
400.067
RMS
399.978
PK2PK
156.224m
Measured Spec Values
Max_VLOAD PASS: Max. Output1 Voltage (24.1127) is less than or equal to Max. Output1 Voltage Spec (25.2)
Min_VLOAD PASS: Min. Output1 Voltage (24.0592) is greater than or equal to Min. Output1 Voltage Spec (22.8)
min_gain_margin PASS: Gain Margin (22.6043) is greater than Min. Gain Margin (12)
min_phase_margin PASS: Phase Margin (61.3474) is greater than Min. Phase Margin (35)
Bode Plot
GAIN
PHASE
SXGPH File simplis_ac25_1494.sxgph
LOAD
VLOAD
ILOAD
SXGPH File simplis_pop25_1460.sxgph
SRC
VSRC
ISRC
SXGPH File simplis_pop25_1450.sxgph
Primary
IDQ1
IDQ2
Im
Ip
Ir
VSW
SXGPH File simplis_pop25_1441.sxgph
Secondary
CLK
ICout
Is1
Is2
Vs
SXGPH File simplis_pop25_1455.sxgph
Other SXGPH Files
default#1483#pop simplis_pop25_1483.sxgph
Modulator#pop simplis_pop25_1488.sxgph